1. Field
Exemplary embodiments of the present invention relate to an e-fuse array circuit, and more particularly, to a structure of an e-fuse array circuit.
2. Description of the Related Art
A general fuse recognizes a data based on whether a fuse is cut or not by a laser. Therefore, a fuse may be programmed in the stage of wafer, but the fuse cannot be programmed once the wafer is mounted in the inside of a package.
To overcome this concern, an e-fuse is used. An e-fuse stores a data by using a transistor and changing the resistance between a gate and a drain/source.
FIG. 1 is schematic diagram illustrating an e-fuse formed of a transistor, the e-fuse operating as a resistor or a capacitor.
Referring to FIG. 1, the e-fuse is formed of a transistor T, and a power source voltage is applied to a gate G while a ground voltage is applied to a drain/source D/S.
When a general power source voltage that the transistor T may tolerate is applied to the gate G, the e-fuse operates as a capacitor C. Therefore, no current flows between the gate G and the drain/source D/S. When a high power source voltage that the transistor T may not tolerate is applied to the gate G, a gate oxide of the transistor T is destroyed to short the coupling between the gate G and the drain/source D/S and the e-fuse operates as a resistor R. Therefore, current flows between the gate G and the drain/source D/S. By taking advantage of these results, data of the e-fuse may be recognized from the resistance value between the gate G and the drain/source D/S of the e-fuse. The data of the e-fuse may be recognized by 1) enlarging the size of the transistor T without additionally performing a sensing operation, or by 2) using an amplifier and sensing the current flowing through the transistor T instead of increasing the size of the transistor T. The two methods, however, have a concern regarding dimensional restriction because the size of the transistor T has to be designed large or an amplifier for amplifying a data has to be added to each e-fuse.
U.S. Pat. No. 7,269,047 discloses a method for decreasing the space occupied by an e-fuse by forming an e-fuse array.
FIG. 2 is a circuit diagram of a conventional cell array 200 including e-fuses.
Referring to FIG. 2, the cell array 200 includes memory cells 201 to 216 that are arrayed in N rows and M columns. The memory cells 201 to 216 include memories M1 to M16 and switches S1 to S16, respectively. The memories M1 to M16 are e-fuses having characteristics of either a resistor or a capacitor based on whether rupturing has occurred or not. In other words, the e-fuses M1 to M16 may be regarded as resistive memories for storing data according to the value of resistance. The switches S1 to S16 electrically connect the memories M1 to M16 with the switches S1 to S16 under the control of word line gate lines WLR1 to WLRN.
Hereafter, it is assumed that a second row is a selected row and an Mth column is a selected column. In other words, it is assumed that a memory cell 208 is a selected memory cell. Voltages applied to the selected memory cell 208 and unselected memory cells 201 to 207 and 209 to 216 during a program/read operation are described below.
Program Operation
A word line gate line WLR2 of the selected row is enabled and the other word line gate lines WLR1 and WLR3 to WLRN are disabled. As a result, switches S5 to S8 are turned on, and the switches S1 to S4 and S9 to S16 are turned off. A high voltage level that could destroy a gate oxide of an e-fuse (which is generally a high voltage generated by supplying a power source voltage) is applied to the program gate line WLP2 of the selected row, and a low-level voltage such as a ground voltage is applied to the other program gate lines WLP1 and WLP3 to WLPN. The selected bit line BLM is coupled with a data access circuit, and the unselected bit lines BL1 to BLM−1 float. The data access circuit drives the selected bit line BLM with a low-level voltage, and programs or ruptures a memory M8 of the selected memory cell 208, when an inputted data is a program data, e.g., ‘1’. When an inputted data is not a program data, for example, when the inputted data is ‘0’, the data access circuit drives the selected bit line BLM with a high-level voltage and does not program the memory M8 of the selected memory cell 208. Because the unselected bit lines BL1 to BLM−1 float, the memories M5 to M7 are not programmed even with a high voltage that is supplied to a gate.
Read Operation
The word line gate line WLR2 of the selected row is enabled, and the other word line gate lines WLR1 and WLR3 to WLRN are disabled. As a result, switches S5 to S8 are turned on, and the switches S1 to S4 and S9 to S16 are turned off. An appropriate level of voltage for a read operation, which is generally a power source voltage, is supplied to a program gate line WLP2 of the selected row, and a low-level voltage such as a ground voltage is supplied to the other program gate lines WLP1 and WLP3 to WLPN. The selected bit line BLM is coupled with a data access circuit, and the unselected bit lines BL1 to BLM−1 float. The data access circuit (not shown) recognizes that the memory M8 is programmed, when current flows through the selected bit line BLM. In other words, the data access circuit recognizes that the data of the selected memory cell 208 is ‘1’. When no current flows through the selected bit line BLM, the data access circuit recognizes that the memory M8 is not programmed. In short, the data access circuit recognizes the data of the selected memory cell 208 as ‘0’.
Herein, one bit line BLM is selected among the multiple bit lines BL1 to BLM for the purpose of illustration, but a plurality of bit lines may be selected at one time. In short, a plurality of memory cells belonging to one row may be programmed/read simultaneously.